MPI12x - MPI Controller & PROFIBUS Slave
Multi Point Interface Controller ASIC
(order code PALF2060, before PA002006)
The profichip MPI12x is a communication chip with processor interface for MPI applications. The MPI12x handles the message and address identification, the data security sequences and the protocol processing for PROFIBUS, which is the underlying transmission protocol. Token handling, error detection and data pre-processing is executed out automatically by the MPI12x, relieving the host processor from all time-critical tasks and time-consuming arithmetic operations. Support of data transmission rates up to 12 Mbit/s, the integration of the PFOFIBus protocol into hardware, 4 KByte communication RAM and the configurable processor interface are features to create high-performance MPI applications. Alternatively, the MPI12x can be used as a Serial Interface Device supporting synchronous and asynchronous standard protocols as well as user defined protocols with data transmission rates up to 12 Mbits/s. Moreover the well-known PROFIBUS Slave Core VPC3+C (extended by DP-V2 service "Clock Synchronisation") is integrated as well.
- MPI communication up to 12Mbit/s
- 4kB integrated SRAM
- Configurable 8-Bit ÂµController Interface
- PROFIBUS Slave core (VPC3+C incl. ClockSync)
- High-Speed Serial Interface core, 16550 compatible, up to 12MBits/s
- 3.3V single supply voltage, 5V tolerant inputs
- Software stack and Evaluation-Kit available
- Package PQFP 44 (RoHS complaint)
The MPI 12x handles the physical layer 1 and the data link layer 2 of the ISO/OSI-reference-model excluding the PROFIBUS line drivers. The processor interface supports the following processor families:
- Intel: 80C31, 80X86
- Siemens: 80C166/165/167
- Motorola: HC11-, HC16-, and HC916
The FLC is connected to the Bus Interface Unit with its 8-bit data bus and a separate 10 bit address bus. The bus mode (synchronous or asynchronous) as well as the microcontroller data format (Intel or Motorola) can be selected by configuration pins.
All registers which configure the chip are located in the module Param. The status register delivers information about the current status of the chip.
Events are stored and asserted by the Interrupt Controller. The events which lead to an interrupt can be locked/unlocked by means of an interrupt mask. The chip has two interrupt lines, one for confirmations and indications and the one for error events. It is also possible to direct all events to only one interrupt line.
The Microsequencer represents the media access state machine. It is responsible for the token handling, generates the request telegrams and filters and processes the indications. If the chip holds the token and there are queued requests the user data is moved from the RAM to the UART and the correct telegram format is generated automatically. The associated response (if applicable) is stored into the dedicated memory area. Incoming indications are checked for plausibility and valid SAP. Only if both conditions are met the chip indicates the telegram to the FLC and sends an answer if available.
Besides the user data blocks the internal 4KByte SRAM holds the List-of-Active-Stations (LAS) and the SAP list as well as some additional parameters and the task queues. It is controlled by a Dual Port RAM Controller that arbitrates the RAM access requests from the Bus Interface Unit and the Microsequencer.
The UART converts the internal parallel data to a continuous serial data stream and vice versa. The transmission technique is asynchronous with 1 start-, 8 data-, parity- and 1 stop bit according to the Profibus Standard. The baud rate can be adjusted between 9.6 KBit/s and 12MBit/s.
The Timer Block contains all necessary timers for observing bus activity and controlling the correct protocol timing.
Alternatively the MPI12x can be used as a Serial Interface Device compatible to a standard 16550 UART with 16 byte receive- and 16 byte transmit-FIFO. Moreover the chip supports Synchronous Serial data transmission with a wide range of configurable formats.
By using the internal SRAM data blocks up to 2KBytes can be sent and received within a single synchronous transmission. For security reasons an automatic CRC generator and checker can be activated. Both the synchronous and the asynchronous operation mode are supporting standard baud rates as well as highspeed data transmission rates up to 12 Mbits/s.